Each process consists of the input port and an extended finite state machine (EFSM) with a sequential behaviour defined by a process graph, which is a sort of state transition diagram. The finite state machine fetches signals from the input port in strict FIFO order except when the order is modified by the save operator (see below). For each signal it performs one transition which will take a short but undefined time.
Signals are messages that the finite state machine consumes. Each signal has a signal type identification which the FSM uses to select the next transition action. In addition, the signal carries the sender identity and possibly some additional data.