Re: SDL-News: Time restriction

Subject: Re: SDL-News: Time restriction
From: Elie Cohen (
Date: Wed Dec 30 1998 - 21:31:01 GMT

The originator of this message is responsible for its content.
-----From "Elie Cohen" <> to sdlnews -----

Rick is quite right when he mentions that "Verifying the timing (that is -
proving that it is correct) would not be an easy task, even with
sophisticated tools".

In its current release of ObjectGEODE, VERILOG has incorporated as part of
the SIMULATOR, a "performance analysis extension". It is described here in


As defined by the ITU-T Z.100 recommendation, SDL does not have a very
realistic notion of time. The standard states that a signal can be delayed
while travelling from one process to another, but the value of that delay
cannot be specified. In the same unrealistic manner, the actions taken
during transitions in the state machines are not assigned any duration.
Finally, SDL does not describe how the system will be
distributed over different CPUs, how the work on each CPU is shared among
tasks, or which priority these tasks assume.

This is not a weakness of SDL when used as a design language, as it forces
the user to model their system without preconception of what the target will
be. This "ignorance" makes the model more portable.
When SDL is used for system analysis, though, the lack of performance
information could lead to invalid architecture decisions. This is the reason
SDL has rarely been used by system designers, who usually prefer dedicated
performance analysis tools.

However the lack of continuity between the architectural design and the
detailed design is very inconvenient, as it forces the users to train
themselves in two different languages, two different methods… and risk
losing part of the architectural design in the translation.

ObjectGEODE offers a few simple extensions to SDL, which enable the system
architects to use SDL in the first place. Note that these extensions are all
implemented in the form of comments, so the models remain standard SDL.

Distribution, Priorities, Duration:

The distribution of the system over several computing resources (CPUs) is
described with the ##NODE comment. This comment can be associated with the
system itself (the top of the hierarchy), when the architect opts for a
single CPU system. If the system is distributed, then
the ##NODE comment will be associated with several blocks and/or processes.

The priority of a task is described by the ##PRIORITY (n) comment, the lower
the number, the higher the priority. The comment is usually associated with
all processes that have to share a common resource.

Finally, duration can be assigned to the action symbols in the Process
transitions. The ##DELAY comment comes in three forms:
· ##DELAY (expression), to assign a fixed duration to an SDL symbol,
· ##DELAY (expression1, expression2), to assign a random duration (uniform
distribution between expression1 and expression2),
· ##DELAY (random_law, parameters), to use a different distribution law.

The delay values assigned by the system architect typically come from actual

The ObjectGEODE simulator performance analysis capabilities

The ##DELAY information makes it possible for the simulator to determine how
long each transition lasts, and to consolidate this information. The user
can obtain results such as the total duration of a transition, or a given
scenario. Furthermore, the simulator can monitor any variable, and provide
the user with minimal, maximal, average value. This information is available
through the ESTIM command of the simulator. For example, the command "ESTIM
E1 = BASE_P!STATE" allows monitoring of the state of process BASE_P.

For variables that can take a large (or infinite) number of values, the
result will be in terms of minimum, maximum, average, and standard
deviation. For example, "ESTIM E3 = LENGTH (BASE_P ! QUEUE)" monitors the
queue length of process BASE_P.

Elie Cohen / Engineering Manager / tel: 972 241 6595 x13 / fax: 972 241 6494
VERILOG, Inc. / 3010 LBJ Fwy, Suite 900 / Dallas TX 75234 /

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